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coolset ? -f3r ice3br1765j off-line smps current mode controller with integrated 650v coolmos ? and startup cell (frequency jitter mode) in dip-8 never stop thinking. power management & supply version 2.3, 19 nov 2012
edition 2012-11-19 published by infineon technologies ag, 81726 munich, germany, ? 2012 infineon technologies ag. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infi neon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact your nearest infineon technologies office (www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact your ne arest infineon technologies office. infineon technologies components may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http:// www.infineon.com coolmos ? , coolset ? are trademarks of infineon technologies ag. coolset ? -f3r ice3br1765j revision history: 2012-11-19 datasheet previous version: 2.2 page subjects (major changes since last revision) 27 revised outline dimension for pg-dip-8 package
type package marking v ds f osc r dson 1) 1) typ @ t j =25c 230vac 15% 2) 2) calculated maximum input power rating at t a =50c, t i =125c and without copper area as heat sink. refer to input power curve for other t a . 85-265 vac 2) ice3br1765j pg-dip-8 ice3br1765j 650v 65khz 1.70 46w 31w coolset ? -f3r ice3br1765j version 2.3 3 19 nov 2012 off-line smps current mode controller with integrated 650v coolmos ? and startup cell (frequency jitter mode) in dip-8 pg-dip-8 description the coolset ? -f3r jitter series (ice3brxx65j) is the latest version of coolset ? -f3. it targets for the off-line battery adapters and low cost smps for lower power range such as application for dvd r/w, dvd combi, blue ray dvd player, set top box, etc. besides inherited the outstanding performance of the coolset ? -f3 in the bicmos technology, active burst mode, auto-restart protection, propagation delay compensation, etc., coolset ? -f3r series has some new features such as built-in soft start time, built-in blanking window, built-in frequency jitter, soft gate driving, etc. in case a longer blanking time is needed for high load application, a simple addition of capacitor to ba pin can serve the purpose. furthermore, an external auto-restart enable feature can provide extra protection when there is a need of immediate stop of power switching. product highlights ? active burst mode to reach the lowest standby power requirements < 50mw ? auto restart protection for overload, overtemperature, overvoltage ? external auto-restart enable function ? built-in soft start and blanking window ? extendable blanking window for high load jumps ? built-in frequency jitter and soft driving for low emi ? green mould compound ? pb-free lead plating; rohs compliant features ? 650v avalanche rugged coolmos ? with built-in startup cell ? active burst mode for lowest standby power ? fast load jump response in active burst mode ? 65khz internally fixed switching frequency ? auto restart protection mode for overload, open loop, vcc undervoltage, overtemperature & overvoltage ? built-in soft start ? built-in blanking window with extendable blanking time for short duration high current ? external auto-restart enable pin ? max duty cycle 75% ? overall tolerance of current limiting 5% ? internal pwm leading edge blanking ? bicmos technology provide wide vcc range ? built-in frequency jitter and soft driving for low emi c vcc c bulk converter dc output + snubber power management pwm controller current mode 85 ... 270 vac typical application r sense ba fb gnd active burst mode auto restart mode control unit - cs vcc startup cell precise low tolerance peak current limitation drain coolset ? ? -f3r (jitter mode) coolmos ?
coolset ? -f3r ice3br1765j table of contents page version 2.3 4 19 nov 2012 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin configuration with pg-dip-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3 improved current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3.1 pwm-op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3.2 pwm-comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.6.2 propagation delay compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.7 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.1 basic and extendable blanking mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.2 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.2.1 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.2.2 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.2.3 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.3 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.7.3.1 auto restart mode with extended blanking ti me . . . . . . . . . . . . . . . . .17 3.7.3.2 auto restart without extended blanking time . . . . . . . . . . . . . . . . . . .18 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.3.4 soft start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.3.5 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.7 coolmos ? section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5 typical coolmos ? performance characteristic . . . . . . . . . . . . . . . . . . .24
coolset ? -f3r ice3br1765j version 2.3 5 19 nov 2012 6 input power curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 schematic for recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . 29
version 2.3 6 19 nov 2012 coolset ? -f3r ice3br1765j pin configuration and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-8 pin symbol function 1 ba extended blanking & auto-restart 2 fb feedback 3 cs current sense/ 650v 1) 1) at t j =110c coolmos ? source 4 drain 650v 1) coolmos ? drain 5 drain 650v 1) coolmos ? drain 6 n.c. not connected 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-8 1 6 7 8 4 3 2 5 gnd ba fb cs vcc n.c. drain drain figure 1 pin configuration pg-dip-8 (top view) note: pin 4 and 5 are shorted 1.2 pin functionality ba (extended blanking & auto-restart) the ba pin combines the functions of extendable bla nking time for over load protection and the external auto-restart enable. the extendable blanking time function is to extend the built -in 20 ms blanking time by adding an external capacitor at ba pin to ground. the external auto-restart enable function is an external access to stop the gate switching and force the ic enter auto-restart mode. it is triggered by pulling down the ba pin to less than 0.33v. fb (feedback) the information about the regulation is provided by the fb pin t o the internal protection unit and to the internal pwm-comparator to control the duty cycle. the fb- signal is the only control signal in case of light load at the active burst mode. cs (current sense) the current sense pin senses the voltage developed on the series resistor inserted in the source of the integrated coolmos ? if voltage in cs pin reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. furthermore the current information is provided for the pwm- comparator to realize the current mode. drain (drain of integrated coolmos ? ) drain pin is the connection to the drain of the int egrated coolmos ? . vcc (power supply) vcc pin is the positive supply of the ic. the operating ran ge is between 10.5v and 25v. gnd (ground) gnd pin is the ground of the controller.
coolset ? -f3r ice3br1765j representative blockdiagram version 2.3 7 19 nov 2012 2 representative blockdiagram internal bias voltage reference oscillator duty cycle max x3.3 current limiting pwm op current mode soft start c2 c1 20.5v 25.5v r fb power management c bk c vcc 85 ... 270 vac c bulk + converter dc output v out pwm comparator c3 4.0v c4 4.0v gate driver 0.72 clock r sense 10k : d1 c6a 3.0v c5 1.35v c10 r s q auto restart mode & g7 & g5 & g9 1 g8 & g1 thermal shutdown 0.9v s1 1 power-down reset cs ba gnd vcc c7 c8 fb pwm section control unit ff1 c12 & 0.34v leading edge blanking 220ns 25k : 2pf 5.0v g10 1pf propagation-delay compensation 5.0v undervoltage lockout v csth g2 - ice3brxx65j / coolset ? ? -f3r ( jitter mode ) snubber vcc drain coolmos ? startup cell c6b & g6 3.5v & g11 active burst mode 0.67v 10.5v 18v #1 # : optional external components; #1 : c bk is used to extend the blanking time #2 : t ae is used to enable the external auto-restart feature freq. jitter 20ms blanking time 20ms blanking time 120us blanking time soft start block soft-start comparator spike blanking 30us t2 3.25k : 5.0v t1 t3 0.6v i bk vcc auto-restart enable signal t ae c9 0.33v 1 ms counter t j >130c #2 figure 2 representative blockdiagram
version 2.3 8 19 nov 2012 coolset ? -f3r ice3br1765j functional description 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction coolset ? -f3r jitter series (ice3brxx65j) is the latest version of the coolset ? -f3 for the lower power application. the particular enhanced features are the built-in features for soft start, blanking window and frequency jitter. it provides the flexibility to increase the blanking window by simply addition of a capacitor in ba pin. in order to further increase the flexibility of the protection feature, an external auto-restart enable features are added. moreover, the proven outstanding features in coolset ? -f3 are still remained such as the active burst mode, propagation delay compensation, modulated gate driving, auto-restart protection for vcc overvoltage, over temperature, over load, open loop, etc. the intelligent active burst mode can effectively obtain t he lowest standby power at light load and no load conditions. after entering the burst mode, there is still a full control of the power conversion to the output through the optocoupler, that is used for the normal pwm control. the response on load jumps is optimized and the voltage ripple on v out is minimized. the v out is on well controlled in this mode. the usually external connected rc-filter in the f eedback line after the optocoupler is integrated in the ic to reduce the external part count. furthermore a high voltage startup cell is integrated int o the ic which is switched off once the undervoltage lockout on-threshold of 18v is exceeded. this startup cell is part of the integrated coolmos ? . the external startup resistor is no longer necessary as this startup cell is connected to the drain. power losses are therefore reduced. this increases the efficiency under light load conditions drastically. adopting the bicmos technology, it can increase the de sign flexibility as the vcc voltage range is increased to 25v. the coolset ? -f3r has a built-in 20ms soft start function. it can further save external component counts. there are 2 modes of blanking time for high load jump s; the basic mode and the extendable mode. the blanking time for the basic mode is set at 20ms while the extendable mode will increase the blanking time by adding an external capacitor at the ba pin in addition to the basic mode blanking time. during this blanking time window the overload detection is disabled. with this concept no further external components are necessary to adjust the blanking window. in order to increase the robustness and safety of the syst em, the ic provides auto restart protection. the auto restart mode reduces the average power conversion to a minimum level under unsafe operating conditions. this is necessary for a prolonged fault condition which could otherwise lead to a destruction of the smps over time. once the malfunction is removed, normal operation is automatically retained after the next start up phase. to make the protection more flexible, an external auto-restart enable pin is provided. when the pin is triggered, the switching pulse at gate will stop and the ic enters the auto-restart mode after the pre-defined spike blanking time. the internal precise peak current control reduces the cost s for the transformer and the secondary diode. the influence of the change in the input voltage on the maximum power limitation can be avoided together with the integrated propagation delay compensation. therefore the maximum power is nearly independent on the input voltage, which is required for wide range smps. thus there is no need for the over-sizing of the smps, e.g. the transformer and the output diode. furthermore, this f3r series implements the f requency jitter mode to the switching clock such that the emi noise will be effectively reduced. 3.2 power management internal bias voltage reference power management 5.0v undervoltage lockout 18v 10.5v power-down reset active burst mode auto restart mode startup cell vcc drain depl. coolmos? soft start block figure 3 power management
coolset ? -f3r ice3br1765j functional description version 2.3 9 19 nov 2012 the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startup cell is biased and starts to charge the external capacitor c vcc which is connected to the vcc pin. this vcc charge current is controlled to 0.9ma by the startup cell. when the v vcc exceeds the on-threshold v ccon =18v the bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore no power losses present due to the connection of the startup cell to the drain voltage. to avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. the switch-off of the controller can only take place when v vcc falls below 10.5v after normal operation was entered. the maximum current consumption before the controller is activated is about 150 p a. when v vcc falls below the off-threshold v ccoff =10.5v, the bias circuit is switched off and the soft start counter is reset. thus it is ensured that at every startup cycle the soft start starts at zero. the internal bias circuit is switched off if auto restart mode is entered. the current consumption is then reduced to 150 p a. once the malfunction condition is removed, this block will then turn back on. the re covery from auto restart mode does not require re-cycling the ac line. when active burst mode is entered, the internal bias is switche d off most of the time but the voltage reference is kept alive in order to reduce the current consumption below 450 p a. 3.3 improved current mode x3.3 pwm op improved current mode 0.67v c8 pwm-latch cs fb r s q q driver soft-start comparator figure 4 current mode current mode means the duty cycle is controlled by the slo pe of the primary current. this is done by comparing the fb signal with the amplified current sense signal. t fb amplified current signal t on t 0.67v driver figure 5 pulse width modulation in case the amplified current sense signal exceeds the fb signal the on-time t on of the driver is finished by resetting the pwm-latch (see figure 5). the primary current is sensed by the external series r esistor r sense inserted in the source of the integrated coolmos ? . by means of current mode regulation, the secondary output voltage is insensitive to the line variations. the current waveform slope will change with the line variation, whic h controls the duty cycle. the external r sense allows an individual adjustment of the maximum source current of the integrated coolmos ? . to improve the current mode during light load con ditions the amplified current ramp of the pwm-op is superimposed on a volta ge ramp, which is built by the switch t2, the voltage source v1 and a resistor r1 (see figure 6). every time the oscillator shuts down for maximum duty cycle limitation the switch t2 is closed by v osc . when the oscillator triggers the gate driver, t2 is opened so that the voltage ramp can start. in case of light load the amplified current ramp is too small to ensure a stable regulation. in that case the voltage ramp is a well defined signal for the comparison with the fb-signal. the duty cycle is then controlled by the slope of the voltage ramp. by means of the time delay ci rcuit which is triggered by the inverted v osc signal, the gate driver is switched-off until it reaches approximately 156ns delay time (see figure 7). it allows the duty cycle to be reduced continuously till 0% by decreasing v fb below that threshold.
pwm op 0.67v 10k : oscillator c8 t 2 r 1 c 1 fb pwm-latch v 1 gate driver voltage ramp v osc soft-start comparator time delay circuit (156ns) x3.3 pwm comparator coolset ? -f3r ice3br1765j functional description version 2.3 10 19 nov 2012 figure 6 improved current mode t t v osc 0.67v fb t max. duty cycle gate driver voltage ramp 156ns time delay figure 7 light load conditions 3.3.1 pwm-op the input of the pwm-op is applied over the internal leading edge blanking to the external sense resistor r sense connected to pin cs. r sense converts the source current into a sense voltage. the sense voltage is amplified with a gain of 3.3 by pwm op. the output of the pwm-op is connected to the voltage source v 1 . the voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the pwm- comparator c8 and the soft-start-comparator (see figure 6). 3.3.2 pwm-comparator the pwm-comparator compares the sensed current signal of the integrated coolmos ? with the feedback signal v fb (see figure 8). v fb is created by an external optocoupler or external transistor in combination with the internal pull-up resistor r fb and provides the load information of the feedback circuitry. when the amplified current signal of the integrated coolmos ? exceeds the signal v fb the pwm-comparator switches off the gate driver. x3.3 pwm op improved current mode pwm comparator cs soft-start comparator 5v c8 0.67v fb optocoupler r fb pwm-latch figure 8 pwm controlling
coolset ? -f3r ice3br1765j functional description version 2.3 11 19 nov 2012 3.4 startup phase s oft-s tart comparator s oft s tart & g7 c7 g ate d river 0.67v x3.3 pwm op cs soft start counter soft start soft start finish s ofts figure 9 soft start in the startup phase, the ic provides a soft start pe riod to control the primary current by means of a duty cycle limitation. the soft start function is a built-in function and it is controlled by an internal counter. . v softs v softs2 v softs1 figure 10 soft start phase when the v vcc exceeds the on-threshold voltage, the ic starts the soft start mode (see figure 10). the function is realized by an internal soft start r esistor, an current sink and a counter. and the amplitude of the current sink is controlled by the counter (see figure 11). 5v r softs soft start counter i 2i 4i softs 8i 32i figure 11 soft start circuit after the ic is switched on, the v sfofts voltage is controlled such that the voltage is increased step- wisely (32 steps) with the increase of the counts. the soft start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. the soft start will be finished in 20ms (t soft-start ) after the ic is switched on. at the end of the soft start period, the current sink is switched off. t v softs32 v softs gate driver t t soft-start figure 12 gate drive signal under soft-start phase
coolset ? -f3r ice3br1765j functional description version 2.3 12 19 nov 2012 within the soft start period , the duty cycle is increasing from zero to maximum gradually (see figure 12). in addition to start-up, soft-start is also activated at each restart attempt during auto restart. t t v softs t v softs32 4.0v t soft-start v out v fb v out t start-up figure 13 start up phase the start-up time t start-up before the converter output voltage v out is settled, must be shorter than the soft- start phase t soft-start (see figure 13). by means of soft-start there is an effective mini mization of current and voltage stresses on the integrated coolmos ? , the clamp circuit and the output overshoot and it helps to prevent saturation of the transformer during start-up. 3.5 pwm section oscillator duty cycle max gate driver 0.75 clock & g9 1 g8 pwm section ff1 r s q soft start comparator pwm comparator current limiting coolmos ? gate frequency jitter soft start block figure 14 pwm section block 3.5.1 oscillator the oscillator generates a fixed frequency of 65khz wit h frequency jittering of 4% (which is 2.6khz) at a jittering period of 4ms. a capacitor, a current source and current sink which d etermine the frequency are integrated. in order to achieve a very accurate switching frequency, the charging and discharging current of the implemented oscillator capacitor are internally trimmed. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.75. once the soft start period is over and when the ic goes i nto normal operating mode, the switching frequency of the clock is varied by the control signal from the soft start block. then the switching frequency is varied in range of 65khz 2.6khz at period of 4ms. 3.5.2 pwm-latch ff1 the output of the oscillator block provides continuous p ulse to the pwm-latch which turns on/off the integrated coolmos ? . after the pwm-latch is set, it is reset by the pwm comparator, the soft start comparator or the current -limit comparator. when it is in reset mode, the output of the driver is shut down immediately.
coolset ? -f3r ice3br1765j functional description version 2.3 13 19 nov 2012 3.5.3 gate driver vcc 1 pwm-latch coolmos ? gate driver gate figure 15 gate driver the driver-stage is optimized to minimize emi and to pr ovide high circuit efficien cy. the switch on speed is slowed down before it reaches the integrated coolmos ? turn on threshold. that is a slope control of the rising edge at the output of the driver (see figure 16). t (internal) v gate 5v ca. t = 130ns figure 16 gate rising slope thus the leading switch on spike is minimized. furt hermore the driver circuit is designed to eliminate cross conduction of the output stage. during power up, when vcc is below the undervoltage lockout threshold v vccoff , the output of the gate driver is set to low in order to disable power transfer to the secondary side. 3.6 current limiting current limiting c10 c12 & 0.34v leading edge blanking 220ns g10 propagation-delay compensation v csth active burst mode pwm latch ff1 10k d1 1pf pwm-op cs figure 17 current limiting block there is a cycle by cycle peak c urrent limiting operation realized by the current-limit comparator c10. the source current of the integrated coolmos ? is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the cs pin. if the voltage v sense exceeds the internal threshold voltage v csth, the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to sup port the immediate shut down of the integrated coolmos ? with very short propagation delay. thus the influence of the ac input voltage on the maximum output power can be reduced to minimal. in order to prevent the current limit from distortions cau sed by leading edge spikes, a leading edge blanking is integrated in the current sense path for the comparators c10, c12 and the pwm-op. the output of comparator c12 is activated by the gate g 10 if active burst mode is entered. when it is activated, the current limiting is reduced to 0.34v. this voltage level determines the maximum power level in active burst mode.
coolset ? -f3r ice3br1765j functional description version 2.3 14 19 nov 2012 3.6.1 leading edge blanking t v sense v csth t leb = 220ns figure 18 leading edge blanking whenever the integrated coolmos ? is switched on, a leading edge spike is generated due to the primary- side capacitances and reverse recovery time of the secondary-side rectifier. this spike can cause the gate drive to switch off unintentionally. in order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of t leb = 220ns. 3.6.2 propagation delay compensation in case of over-current detection, there is always propagation delay to switch off the integrated coolmos ? . an overshoot of the peak current i peak is induced to the delay, which depends on the ratio of di/ dt of the peak current (see figure 19). t i sense i limit t propagation delay i overshoot1 i peak1 signal1 signal2 i overshoot2 i peak2 figure 19 current limiting the overshoot of signal2 is larger than of signal1 due t o the steeper rising waveform. this change in the slope depends on the ac input voltage. propagation delay compensation is integrated to reduce the overshoot due to di/dt of the rising primary current. thus the propagation delay time between exceeding the current sense threshold v csth and the switching off of the integrated coolmos ? is compensated over temperature within a wide range. current limiting is then very accurate. for example, i peak = 0.5a with r sense = 2. the current sense threshold is set to a static voltage level v csth =1v without propagation delay compensation. a current ramp of di/dt = 0.4a/s, or dv sense /dt = 0.8v/s, and a propagation delay time of t propagation delay =180ns leads to an i peak overshoot of 14.4%. with the propagation delay compensation, the overshoot is only around 2% (see figure 20). 0,9 0,95 1 1,05 1,1 1,15 1,2 1,25 1,3 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 with compensation without compensation dt dv sense s v p sense v v figure 20 overcurrent shutdown the propagation delay compensation is realized by me ans of a dynamic threshold voltage v csth (see figure 21). in case of a steeper slope the switch off of the driver is earlier to compensate the delay. t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t figure 21 dynamic voltage threshold v csth
coolset ? -f3r ice3br1765j functional description version 2.3 15 19 nov 2012 3.7 control unit the control unit contains the functions for active burst mode and auto restart mode. the active burst mode and the auto restart mode both have 20ms internal blanking time. for the auto restart mode, a further extendable blanking time is achieved by adding external capacitor at ba pin. by means of this blanking time, the ic avoids entering into these two modes accidentally. furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally. 3.7.1 basic and extendable blanking mode c3 4.0v c4 4.0v c5 1.35v & g5 & g6 0.9v s1 1 g2 control unit active burst mode auto restart mode 5.0v ba fb c bk 20ms blanking time 20ms blanking time spike blanking 3 0us # i bk figure 22 basic and extendable blanking mode there are 2 kinds of blanking mode; basic mode and t he extendable mode. the basic mode is just an internal set 20ms blanking time while the extendable mode has an extra blanking time by connecting an external capacitor to the ba pin in addition to the pre- set 20ms blanking time. for the extendable mode, the gate g5 is blocked even though the 20ms blanking time is reached if an external capacitor c bk is added to ba pin. while the 20ms blanking time is passed, the switch s1 is opened by g2. then the 0.9v clamped voltage at ba pin is charged to 4.0v through the internal i bk constant current. g5 is enabled by comparator c3. after the 30us spike blanking time, the auto restart mode is activated. for example, if c bk = 0.22uf, i bk = 13ua blanking time = 20ms + c bk x (4.0 - 0.9) / i bk = 72ms in order to make the startup properly, the maximum c bk capacitor is restricted to less than 0.65uf. the active burst mode has basic blanking mode only wh ile the auto restart mode has both the basic and the extendable blanking mode. 3.7.2 active burst mode the ic enters active burst mode under low load con ditions. with the active burst mode, the efficiency increases significantly at light load conditions while still maintaining a low ripple on v out and a fast response on load jumps. during active burst mode, the ic is controlled by the fb signal. since the ic is always active, it can be a very fast response to the quick change at the fb signal. the start up cell is kept off in order to minimize the power loss. c4 4.0v c6a 3.5v c5 1.35v fb control unit active burst mode internal bias & g10 current limiting & g6 c6b 3.0v & g11 20 ms blanking time figure 23 active burst mode the active burst mode is located in the control unit. fig ure 23 shows the related components. 3.7.2.1 entering active burst mode the fb signal is kept monitoring by the comparator c5. du ring normal operation, the internal blanking time counter is reset to 0. once the fb signal falls below 1.35v, it starts to count. when the counter reach 20ms
coolset ? -f3r ice3br1765j functional description version 2.3 16 19 nov 2012 and fb signal is still below 1.35v, the system enters the active burst mode. this time window prevents a sudden entering into the active burst mode due to large load jumps. after entering active burst mode, a burst flag is set and the internal bias is switc hed off in order to reduce the current consumption of the ic to approx. 450ua. it needs the application to enforce the vcc voltage ab ove the undervoltage lockout level of 10.5v such that the startup cell will not be switched on accidentally. or otherwise the power loss will increase drastically. the minimum vcc level during active burst mode depends on the load condition and the application. the lowest vcc level is reached at no load condition. 3.7.2.2 working in active burst mode after entering the active burst mode, the fb voltage rises as v out starts to decrease, which is due to the inactive pwm section. the comparator c6a monitors the fb signal. if the voltage level is larger than 3.5v, the internal circuit will be activated; the internal bias circuit resumes and starts to provide switching pulse. in active burst mode the gate g10 is released and the current limit is reduced to 0.34v, which can reduce the conduction loss and the audible noise. if the load at v out is still kept unchanged, the fb signal will drop to 3.0v. at this level the c6b deactivates the internal circuit again by switching off the internal bias. the gate g11 is active again as the burst flag is set after entering active burst mode. in active burst mode, the fb voltage is changing like a saw tooth between 3.0v and 3.5v (see figure 24). 3.7.2.3 leaving active burst mode the fb voltage will increase immediately if there is a hig h load jump. this is observed by the comparator c4. since the current limit is app. 34% during active burst mode, it needs a certain load jump to rise the fb signal to exceed 4.0v. at that time the comparator c4 resets the active burst mode control which in turn blocks the comparator c12 by the gate g10. the maximum current can then be resumed to stabilize the v out. 1.35v 3.5v 4.0v v fb t t 0.34v 1.03v v cs 10.5v v vcc t t 450ua i vcc t 2.7ma v out t 20ms blanking time current limit level during active burst mode 3.0v entering active burst mode leaving active burst mode blanking timer figure 24 signals in active burst mode
coolset ? -f3r ice3br1765j functional description version 2.3 17 19 nov 2012 3.7.3 protection modes the ic provides auto restart mode as the protection feature. auto restart mode can prevent the smps from destructive states. the following table shows the relationship between possible system failures and the corresponding protection modes. vcc overvoltage auto restart mode overtemperature auto restart mode overload auto restart mode open loop auto restart mode vcc undervoltage auto restart mode short optocoupler auto restart mode auto restart enable auto restart mode before entering the auto restart protection mode, some of the protections can have extended blanking time to delay the protection and some needs to fast react and will go straight to the protection. overload and open loop protection are the one can have extended blanking time while vcc overvoltage, over temperature, vcc undervoltage, short opto-coupler and external auto restart enable will go to protection right away. after the system enters the auto-restart mode, the ic will be off. since there is no more switching, the vcc voltage will drop. when it hits the vcc turn off threshold, the start up cell will turn on and the vcc is charged by the startup cell current to vcc turn on threshold. the ic is on and the startup cell will turn off. at this stage, it will enter the startup phase (soft start) with switching cycles. after the start up phase, the fault condition is checked. if the faul t condition persists, the ic will go to auto restart mode again. if, otherwise, the fault is removed, normal operation is resumed. 3.7.3.1 auto restart mode with extended bl anking time figure 25 auto restart mode in case of overload or open loop, the fb exceeds 4 .0v which will be observed by comparator c4. then the internal blanking counter starts to count. when it reaches 20ms, the switch s1 is released. then the clamped voltage 0.9v at v ba can increase. when there is no external capacitor c bk connected, the v ba will reach 4.0v immediately. when both the input signals at and gate g5 is positive, the auto restart mode will be activated after the extra spike blanking time of 30us is elapsed. however, when an extra blanking time is needed, it can be achieved by adding an external capacitor, c bk . a constant current source of i bk will start to charge the capacitor c bk from 0.9v to 4.0v after the switch s1 is released. the charging time from 0.9v to 4.0v are the extendable blanking time. if c bk is 0.22uf and i bk is 13ua, the extendable blanking time is around 52ms and the total blanking time is 72ms. in combining the fb and blanking time, there is a blanking window generated which prevents the system to enter auto restart mode due to large load jumps. c3 4.0v c4 4.0v & g5 0.9v s1 1 g2 control unit auto restart mode 5.0v ba fb c bk 20ms blanking time spike blanking 3 0us # i bk
c1 20.5v spike blanking 30us & g1 thermal shutdown t j >140c auto restart mode vcc c4 4.0v voltage reference control unit auto restart mode reset v vcc < 10.5v fb c2 120us blanking time vcc 25.5v softs_period ba auto-restart enable signal t ae c9 8us blanking time 0.3v stop gate drive 1ms counter uvlo coolset ? -f3r ice3br1765j functional description version 2.3 18 19 nov 2012 3.7.3.2 auto restart without extended blanking time figure 26 auto restart mode there are 2 modes of v cc overvoltage protection; one is during soft start and the other is at all conditions. the first one is v vcc voltage is > 20.5v and fb is > 4.0v and during soft_start period and the ic enters auto restart mode. the vcc voltage is observed by comparator c1 and c4. the fault conditions are to detect the abnormal operating during start up such as open loop during light load start up, etc. the logic can eliminate the possible of entering auto restart mode if there is a small voltage overshoots of v vcc during normal operating. the 2nd one is v vcc >25.5v and last for 120us and the ic enters auto restart mode. this 25.5v vcc ovp protection is inactivated during burst mode. the thermal shutdown block monitors the junction t emperature of the ic. after detecting a junction temperature higher than 130c, the auto restart mode is entered. in case the pre-defined auto-restart features are not suf ficient, there is a customer defined external auto- restart enable feature. this function can be triggered by pulling down the ba pin to < 0.33v. it can simply add a trigger signal to the base of the externally added transistor, t ae at the ba pin. when the function is enabled, the gate drive switching will be stopped and then the ic will enter auto-restart mode if the signal persists. to ensure this auto-restart function will not be mis-triggered during start up, a 1ms delay time is implemented to blank the unstable signal. vcc undervoltage is the vcc voltage drop below vcc turn off threshold. then the ic will turn off and the start up cell will turn on automatically. and this leads to auto restart mode. short optocoupler also leads to vcc undervoltage as t here is no self supply after activating the internal reference and bias.
coolset ? -f3r ice3br1765j electrical characteristics version 2.3 19 19 nov 2012 4 electrical characteristics note: all voltages are measured with respect to ground (pin 5). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. switching drain current, pulse width t p limited by t j =150c i s - 4.03 a pulse drain current, pulse width t p limited by t j =150c i d_puls - 6.12 a avalanche energy, repetitive t ar limited by max. t j =150c 1) 1) repetitive avalanche causes additional power losses that can be calculated as p av = e ar * f e ar - 0.15 mj avalanche current, repetitive t ar limited by max. t j =150c 1) i ar - 1.5 a vcc supply voltage v vcc -0.3 27 v fb voltage v fb -0.3 5.5 v ba voltage v ba -0.3 5.5 v cs voltage v cs -0.3 5.5 v junction temperature t j -40 150 q c controller & coolmos ? storage temperature t s -55 150 q c thermal resistance junction -ambient r thja - 90 k/w soldering temperature, wavesoldering on ly allowed at leads t sold - 260 q c 1.6mm (0.063in.) from case for 10s esd capability (incl. drain pin) v esd - 2 kv human body model 2) 2) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k : series resistor) note: absolute maximum ratings are defined as rating s, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 4 ( v cc) is discharged before assembling the application circuit.t a =25 q c unless otherwise specified.
coolset ? -f3r ice3br1765j electrical characteristics version 2.3 20 19 nov 2012 4.2 operating range note: within the operating range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 25 v max value limited due to vcc ovp junction temperature of cont roller t jcon -25 130 c max value limited due to thermal shu t down of controller junction temperature of cool mos ? t jcoolmos -25 150 q c 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 q c t o 125 q c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 18 v is assumed. parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 150 250 p a v vcc =17v vcc charge current i vcccharge1 - - 5.0 ma v vcc = 0v i vcccharge2 0.55 0.9 1.60 ma v vcc = 1v i vcccharge3 - 0.7 - ma v vcc =17v leakage current of start up cell and coolmos ? i startleak - 0.2 50 p a v drain = 450v at t j =100c supply current with inactive gate i vccsup1 - 1.5 2.5 ma supply current with active gate i vccsup2 - 2.7 3.4 ma i fb = 0a supply current in auto restart mode with inactive ga te i vccrestart - 250 - p a i fb = 0a supply current in active burst mode with inactive gate i vccburst1 - 450 950 p a v fb = 2.5v i vccburst2 - 450 950 p a v vcc = 11.5v, v fb = 2.5v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 17.0 9.8 - 18.0 10.5 7.5 19.0 11.2 - v v v
version 2.3 21 19 nov 2012 coolset ? -f3r ice3br1765j electrical characteristics 4.3.2 internal voltage reference parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 4.90 5.00 5.10 v measured at pin fb i fb = 0 4.3.3 pwm section parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency f osc1 56.5 65.0 73.5 khz f osc2 59.8 65.0 70.2 khz t j = 25c frequency jittering range f jitter - 2.6 - khz t j = 25c frequency jittering period t jitter - 4.0 - ms t j = 25c max. duty cycle d max 0.70 0.75 0.80 min. duty cycle d min 0 - - v fb < 0.3v pwm-op gain a v 3.1 3.3 3.5 voltage ramp offset v offset-ramp - 0.67 - v v fb operating range min level v fbmin - 0.5 - v v fb operating range max level v fbmax - - 4.3 v cs=1v, limited by compar ator c4 1) 1) the parameter is not subjected to production test - verified by design/characterization fb pull-up resistor r fb 9 15.4 22 k: 4.3.4 soft start time parameter symbol limit values unit test condition min. typ. max. soft start time t ss - 20.0 - ms
coolset ? -f3r ice3br1765j electrical characteristics version 2.3 22 19 nov 2012 4.3.5 control unit parameter symbol limit values unit test condition min. typ. max. clamped v ba voltage during normal operating mode v baclmp 0.85 0.9 0.95 v v fb = 4v blanking time voltage limit for compa rator c3 v bkc3 3.85 4.00 4.15 v over load & open loop detection limi t for comparator c4 v fbc4 3.85 4.00 4.15 v active burst mode level for compa rator c5 v fbc5 1.25 1.35 1.45 v active burst mode level for compa rator c6a v fbc6a 3.35 3.50 3.65 v after active burst mode is entered active burst mode level for compa rator c6b v fbc6b 2.88 3.00 3.12 v after active burst mode is entered overvoltage detection limit for compa rator c1 v vccovp1 19.5 20.5 21.5 v v fb = 5v overvoltage detection limit for compa rator c2 v vccovp2 25.0 25.5 26.5 v auto-restart enable level at ba pin v ae 0.25 0.33 0.4 v >30 p s charging current at ba pin i bk 10.0 13.0 16.9 p a charge starts after the built -in 20ms blanking time elapsed thermal shutdown 1) 1) the parameter is not subjected to production test - ve rified by design/characterization. the thermal shutdown temperature refers to the junction temperature of the controller. t jsd 130 140 150 c controller built-in blanking time for over load protection or enter active burst mode t bk - 20 - ms without external ca pacitor at ba pin inhibit time for auto-restart en able function during start up t ihae - 1.0 - ms count when vcc>18v spike blanking time before auto- rest art protection t spike - 30 - p s note: the trend of all the voltage levels in the control unit is the same regarding the deviation except v vccovp .
coolset ? -f3r ice3br1765j electrical characteristics version 2.3 23 19 nov 2012 4.3.6 current limiting parameter symbol limit values unit test condition min. typ. max. peak current limitation (incl. propagation delay) v csth 0.96 1.03 1.10 v d v sense / d t = 0.6v/ p s (see figure 20) peak current limitation during ac tive burst mode v cs2 0.29 0.34 0.38 v leading edge blanking t leb - 220 - ns cs input bias current i csbias -1.5 -0.2 - p a v cs =0v 4.3.7 coolmos ? section parameter symbol limit values unit test condition min. typ. max. drain source breakdown voltage v (br)dss 650 - - v t j = 110c refer to figure 30 for ot her v (br)dss in different t j drain source on-resistance r dson - - 1.70 3.57 1.96 4.12 : : t j = 25c t j =125c 1) 1) the parameter is not subjected to production test - verified by design/characterization at i d = 1.5a effective output capacitance, energy re lated c o(er) - 11.63 - pf v ds = 0v to 480v 1) rise time t rise - 30 2) 2) measured in a typical flyback converter application - ns fall time t fall - 30 2) - ns
coolset ? -f3r ice3br1765j typical coolmos ? performance characteristic version 2.3 24 19 nov 2012 5 typical coolmos ? performance characteristic safe operating area for ice3a(b)r1765j i d = f ( v ds ) parameter : d = 0, t c = 25deg.c 0.001 0.01 0.1 1 10 1 10 100 1000 v ds [v] i d [a] dc tp = 100ms tp = 0.1ms tp = 1ms tp = 10ms tp = 1000ms figure 27 safe operating area (soa) curve for ice3br1765j soa temperature derating coefficient curve ( package dissipation ) for f3 & f2 coolset 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 ambient/case temperature ta/tc [deg.c] ta : dip, tc : to220 soa temperature derating coefficient [%] figure 28 soa temperature derating coefficient curve
allowable power dissipation for f3 coolset in dip-8 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 20 40 60 80 100 120 140 ambient temperature, t a [deg.c] allowable power dissipation, p tot [w] coolset 3 ice3b165j tpical coolos performance caracteristic version 2.3 25 1 o 2012 figure 29 power dissipation; p tot =f(t a ) 540 580 620 660 700 -60 -20 20 60 100 140 180 t j [c] v br(dss) [v] figure 30 drain-source breakdown voltage; v br(dss) =f(t j )
coolset ? -f3r ice3br1765j input power curve version 2.3 26 19 nov 2012 6 input power curve two input power curves giving the typical input power versus ambient temperature are showed below; vin=85vac~265vac (figure 31) and vin=230vac+/-15% (f igure 32). the curves are derived based on a typical discontinuous mode flyback model which considers either 50% maximum duty ratio or 100v maximum secondary to primary reflected voltage (higher priority). the calcul ation is based on no copper area as heatsink for the device. the input power already includes the power loss at input common mode choke, bridge rectifier and the coolmos.the device saturation current ( i d_puls @ t j =125c) is also considered. to estimate the output power of the device, it is simply mult iplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. for example, a wide range input voltage (figure 31), operating temperature is 50c, estimated efficiency is 85%, then the estimated output power is 26w (31w * 85%). ambient temperature [c] input power (85~265vac) [w] pi-005-ice3br1765j_85vac 0 4 8 12 16 20 24 28 32 36 40 0 102030405060708090100110120130 figure 31 input power curve vin=85~265vac; p in =f(t a ) ambient temperature [c] input power (230vac) [w] pi-006-ice3br1765j_230vac 0 6 12 18 24 30 36 42 48 54 60 0 10 20 30 40 50 60 70 80 90 100 110 120 130 figure 32 input power curve vin=230vac+/-15%; p in =f(t a )
coolset ? -f3r ice3br1765j outline dimension version 2.3 27 19 nov 2012 7 outline dimension pg-dip-8 (plastic dual in-line outline) figure 33 pg-dip-8 (pb-free lead plating plastic dual-in-line outline)
coolset ? -f3r ice3br1765j marking version 2.3 28 19 nov 2012 8 marking marking figure 34 marking for ice3br1765j
coolset ? -f3r ice3br1765j schematic for recommended pcb layout version 2.3 29 19 nov 2012 9 schematic for recommended pcb layout c11 bulk cap r11 d11 c12 ic12 r12 c13 c16 c15 c14 d13 r14 r23 r22 ic21 c23 r24 c22 r21 r25 gnd vo d21 c21 f3 coolset schematic for recommended pcb layout r13 z11 tr1 n l br1 c2 y-cap c3 y-cap c1 x-cap l1 fuse1 c4 y-cap gnd spark gap 3 spark gap 4 d11 spark gap 1 spark gap 2 fb cs gnd nc ba vcc f3 drain coolset ic11 * figure 35 schematic for recommended pcb layout general guideline for pcb layout design using f3/f3r coolset ? (refer to figure 35): 1. ?star ground ?at bulk capacitor ground, c11: ?star ground ?means all primary dc grounds should be connected to the ground of bulk capacitor c11 separa tely in one point. it can reduce the switching noise going into the sensit ive pins of the coolset ? device effectively. the primary dc grounds include the followings. a. dc ground of the primary auxiliary winding in power transformer, tr1, and ground of c16 and z11. b. dc ground of the current sense resistor, r12 c. dc ground of the coolset ? device, gnd pin of ic11; the signal grounds from c13, c14, c15 and collector of ic12 should be connected to the gnd pin of ic11 and then ?star ?connect to the bulk capacitor ground. d. dc ground from bridge rectifier, br1 e. dc ground from the bridging y-capacitor, c4 2. high voltage traces clearance: high voltage traces should keep enough spacing to the n earby traces. otherwise, arcing would incur. a. 400v traces (positive rail of bulk c apacit or c11) to nearby trace: > 2.0mm b. 600v traces (drain voltage of coolset ? ic11) to nearby trace: > 2.5mm 3. filter capacitor close to the controller ground: filter capacitors, c13, c14 and c15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switch ing noise coupled into the controller. guideline for pcb layout design when >3kv lightning surge test applied (refer to figure 35): 1. add spark gap spark gap is a pair of saw-tooth like copper plate f acing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. spark gap 3 and spark gap 4, input common mode choke, l1: gap separation is around 1.5mm (no safety concern)
coolset ? -f3r ice3br1765j schematic for recommended pcb layout version 2.3 30 19 nov 2012 b. spark gap 1 and spark gap 2, live / neutral to ground: these 2 spark gaps can be used when the lightning surge requirement is >6kv. 230vac input voltage application, the gap separation is around 5.5mm 115vac input voltage application, the gap separation is around 3mm 2. add y-capacitor (c2 and c3) in the live and neutral to ground even though it is a 2-pin input 3. add negative pulse clamping diode, d11 to the current sense resistor, r12: the negative pulse clamping diode can reduce the nega tive pulse going into the cs pin of the coolset ? and reduce the abnormal behavior of the coolset ? . the diode can be a fast speed diode such as in4148. the principle behind is to drain the high surge voltage from live/neutral to ground without passing through the sensitive components such as the primary controller, ic11.
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